5000 Orchard Park, Apt-5812, Davis-95616, CA. Tel: (530) 746-8066. [email protected]
Accomplished, dynamic professional with years of experience conducting high-level scientific research and development. Motivated by challenge, with strong analytical approach to problem solving. Team player integral to success of numerous industrial and research projects.
Ph.D in Electrical and Computer Engineering, UC-Davis. (Expected – February -2012; GPA: 3.53) Major: Embedded Systems, Minor: Computer Network Security
M.Sc in Computer Engineering, KFUPM, Dhahran, KSA. GPA: 3.72. (June-2005) Major: Synthesis of Digital Systems, Minor: Non-deterministic evolutionary algorithms and optimization
Bachelors in Computer Systems Engineering; NEDUET, Pakistan. (April-2001)
Sequential & Parallel Programming: Extensive exposure in C/C++ based single and multi-threaded
programming and algorithmic design and analysis.
Embedded Systems: Strong background in developing hardware-software based co-designed embedded
(digital) systems, hardware accelerators and co-processors.
Languages and Scripting: C/C++, Perl/Python scripting, Verilog HDL, VHDL, Assembly languages. Keywords: Computer Architecture, Algorithms, Parallel Programming, FPGAs, ASICS, Network
Hardware Design Engineer at Digitek-Mantero Networks, Pakistan – Maryland, USA (Jan-August, ‘06)
Team leader: Design, development and verification of next generation FPGA based communication
Extended the abilities of OPENCORES’ PCI core for internal integration project.
Lawrence Livermore National Laboratory (Computational Intern: Jan. – April & July – August 2010)
Design and FPGA based development of next generation Traffic Classification solutions. ()
Laboratory of Embedded and Programmable Systems (http://leps.ece.ucdavis.edu), UC-Davis (Sept’06 - )
Hardware/software co-designed programmable solutions for streaming closed-loop network traffic inspection and analysis. Publication [1,2,4,6] Developed novel reconfiguration paradigms for partial dynamic reconfiguration of FPGAs.  Design and developed on-chip network of processors for heavy-hitters identification in IP-networks.
Laboratory of Robust and Ubiquitous Networking (http://www.ece.ucdavis.edu/rubinet/), UC-Davis (Sept’06 - )
Designed and developed streaming algorithms for online measurement and analysis of streaming
network traffic and detection of anomalies for local and distributed networks [1,2].
Teaching Assistant at Department of Electrical and Computer Engineering, UC-Davis
Led weekly lab sections and held office hours for a number of digital design, senior design project,
computer architecture and assembly language coursework.
Helped develop the contents for senior digital design project. 
King Fahd University of Petroleum & Minerals (July 2002 – December 2005)
Finite State Machine State Assignment for Area, Power Minimization and Increased Testability  TAed various digital design coursework and developed FPGA CAD Laboratory in Computer Engineering Department, KFUPM (2003)
NED University of Engineering & Technology
FPGA based Pipelined Implementation of JPEG Encoder in Verilog RTL . Atmel Microcontroller and PC based Microcontroller Flash Programmer 2D/3D Graph Plotter in C language.
UC-Davis OGS Fellowship, September 2006 College of Computer Science (KFUPM) ‘Special Contribution Award’ for CAD Laboratory
KFUPM Fellowship for pursuing Masters in Computer Engineering, 2002. HSC merit Scholarship for securing 13th position in HSC-Examinations, 1996 President of Pakistan Talent Farming Scholarship for securing 14th position in Presidential Talent
 F. Khan, C-N, Chuah, and S. Ghiasi, “A Dynamically Reconfigurable System for Closed-Loop
Measurements of Network Traffic”, manuscript under review in Transaction on Computers.
 F. Khan, N. Hosein, C-N. Chuah, and S. Ghiasi, "Streaming Solutions For Fine-Grained Network
Traffic Measurements And Analysis," ACM/IEEE Symposium on Architectures for Networking and Communication Systems (ANCS), October 2011.
 Soheil Ghiasi, Matin Hashemi, Volodymyr Khibin, Faisal Khan, “Puzzle Solver Accelerators Make
Excellent Capstone Design Projects”, 2011 International Conference on Microelectronic System Education (MSE), San Diego, CA, USA.
 F. Khan, M. Gokhale, and C-N. Chuah, "FPGA-based Network Traffic Analysis using Traffic
Dispersion Patterns," International Conference on Field Programmable Logic and Applications (FPL), August 2010, Milan Italy.
 Faisal Khan, Nicholas Hosein, Scott Vernon, Soheil Ghiasi, "BURAQ: A Dynamically Reconfigurable
System for Stateful Measurement of Network Traffic", 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM-2010
 Faisal N. Khan, Lihua Yuan, C-N. Chuah, Sohiel Ghiasi, “A Programmable Architecture for Scalable
and Real-time Network Traffic Measurements”, In Proceedings of the 4th ACM/IEEE Symposium on Architectures For Networking and Communications Systems, ANCS-2008
 Aiman El-Maleh, Sadiq M. Sait and Faisal N. Khan, “Finite State Machine State Assignment for Area
and Power Minimization”, In Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS-2006
 Faisal N. Khan, “A VLSI Implementation of Fully Pipelined Baseline JPEG Encoder”, IEEE conference on ‘Technology Extravaganza’, 11th August 2000, NEDUET (IEEE Record No. 8204).
Institute of Electrical and Electronics Engineers (IEEE) (2006 – Present) IEEE – Computer Society (2006 – Present)
Kuntajakoselvittäjän kysymykset/MAL ja kuntarakenteet/Vastauskooste Millainen oli tilanne maankäytön, asumisen ja liikenteen kehittämisen ja yh- teensovittamisen osalta ennen Jyväskylän, Jyväskylän maalaiskunnan ja Kor- pilahden kuntien yhdistymistä? Hankasalmi on kuulunut jo ennen em. kuntaliitoksia verkkariryhmään jossa maankäytön ja asumisen kysymyksiä selvitelt
Breastfeeding Mastitis/Plugged Duct Information Between 1% and 5% of nursing mothers experience inflammation and infection of the breast tissue and/or milk ducts in a portion of one or both breasts. Mothers at risk for (bacterial) mastitis are those who experience: IMPORTANT • Sudden decrease in nursing frequency leading to milk stasis • Sudden increase in maternal activity �